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3,356,858 on the surface 86 of the silicon body 83 and is located in part between associated drain and source contacts. The drain contacts 87 and 93, as well as the source contacts 88 and 94, are metallized with a suitable metallic substance, such as aluminum. Source contact 93 also serves as the metal interconnection between P-type region 90 and N-type region 92.

A metallic gate 96 of preferably aluminum for the P-type field-effect semiconductor device 82 is disposed in contact with the portion of the insulated layer 95 located between the drain 87 and the gate 88. Similarly, a metallic gate 97 of preferably aluminum for the N-type field-effect semiconductor device 81 is disposed in contact with the portions of the insulated layer 95 located between the drain 93 and the source 94.

The P-type insulated gate field-effect semiconductor device 82 operates and functions in the manner previously described in detail for the P-type insulated gate field-effect semiconductor device 30. Likewise, the N-type external insulated gate field-effect semiconductor device 81 operates and functions in the manner previously described in detail for the N-type external insulated gate field-effect semiconductor device 10.

A lead 87a is attached to the source electrode 87 of the semiconductor device 82 and is connected to a source of electrical energy. Through this arrangement, a +V biasing potential is applied to the source electrode 87. In a like manner, a lead 93a is connected to the source electrode 93 of the semiconductor device 81 and is connected to the source of electrical energy. Through this arrangement, a -V biasing potential is impressed on the drain electrode 93. It is to be noted that all junctions will be either at zero bias or at reverse bias, but it will never be at forward bias. The gates 96 and 97 of the semiconductor devices 82 and 81, respectively, are connected in common over a conductor 100. Fed to the conductor 100 is an input signal Vi. A common conducting strip 101 is attached to the source electrodes 88 and 94 of the semiconducting devices 82 and 81, respectively. A lead 102 is connected to the conducting strip 101 for transmitting the output signal therefrom.

From the foregoing, it is observed that an inverter circuit 81a is formed from the semiconductor unitary structure 80. The operation of the inverter or switching circuit 81a will now be described. When the input signal Vi, which is impressed on the gates 96 and 97, is equal to or greater than the positive critical potential, the P-type field-effect semiconductor device 82 will not conduct and the N-type field-effect semiconductor device 81 will conduct. The output voltage Vo is, therefore, negative.

When the input signal Vi, which is impressed on the gates 96 and 97, is equal to or more negative than the critical potential, the N-type field-effect semiconductor device 81 will not conduct and the P-type field-effect semiconducter device 82 will conduct. The output voltage Vo is positive.

Therefore, the circuit 81a produces a switching or inverting action without employing any passive load component, such as a load resistor. Further, the field-effect semiconductor device 82, a majority hole carrier device, is employed as the active load for the field-effect semi-conductor device 81, a majority electron carrier device. The converse is also true, since the field-effect semiconductor device 82, a majority electron carrier device, is used as the active load for the field-effect semiconductor device 81, a majority hole carrier device.

The complementary N and P type insulated gate field-effect semiconductor devices are employed by the circuits of the present invention to produce low stand-by power systems. Through the exclusive use of these devices, the high speed switching circuits of the present invention dissipate appreciable power only during the switching transient. The above-described circuits of the present invention are relatively unaffected in performance by ambient temperatures up to approximately 150 degrees centigrade, since they employ only majority carrier devices which are relatively temperature-independent. Systems employing the circuits of the present invention perform in spite of large temperature gradients within the system.

Because of the voltage-controlled nature of the active elements, there are no problems of unequal sharing by the next logic stage, at least at low speeds. Thus, the fan out capabilities are extremely favorable. Further, the circuits of the present invention offer large voltage swings and low dynamic impedance in both states. This is desirable for immunity against noise pulses.

It is to be understood that modifications and variations of the embodiments of the invention disclosed herein may be resorted to without departing from the spirit of the invention and the scope of the appended claims.

Having thus described my invention, what I claim and desire to protect by Letters Patent is:

1. A combinational switching circuit comprising a first semiconductor body of one conductivity type with a plurality of spaced diffused regions of a conductivity type opposite to said body and forming PN junctions therewith extending to a surface of said body, a first pair of source and drain electrodes on said body adjacent two of said diffused regions at said surface, a first insulating layer on said surface of said body between said drain and source electrodes, a first gate electrode adjacent said first insulating layer, a pair of spaced diffused regions of said one conductivity type formed within a third one of said plurality of spaced diffused regions and forming PN junctions with said third 30 diffused region extending to said surface, a second pair of source and drain electrodes on said pair of spaced diffused regions, a second insulating layer on the surface of said third diffused region between said second pair of source and drain electrodes, a second gate electrode on said second insulating layer, means for applying biasing potentials of the same polarity to both of said gate electrodes.

2. A circuit comprising a first insulated gate field-effect transistor having a substrate of one conductivity type, an insulating layer adjacent said substrate, a metal layer upon said insulating layer opposite said substrate, and a channel region adjacent said insulating layer having a conductivity type opposite said substrate upon application of a first pre-determined bias voltage to said metal layer, thereby forming a PN junction between said substrate and said channel region, source and drain electrodes on opposite ends of said channel region, a second insulated gate field-effect transistor having a substrate of said opposite conductivity type, an insulating layer adjacent said substrate, a metal layer upon said insulating layer opposite said substrate, and a channel region adjacent said insulating layer having said one conductivity type upon application of a second predetermined bias voltage to said metal layer of polarity opposite to said first predetermined bias voltage, source and drain electrodes on opposite ends of said channel region, one of said source and drain electrodes of said first insulated gate field-effect transistor being coupled to one of said source and drain electrodes of said second insulated field-effect transistor, a means for applying a fixed bias voltage across the other of said source and drain electrodes of said first and second insulated field-effect transistors, and a means for applying a voltage signal of a single predetermined polarity to both of said metal layers of said first and second insulated gate field-effect transistors adapted to render said first insulated gate field-effect transistor conductive between its source and drain electrodes while rendering said second insulated gate field-effect transistor non-conductive between its source and drain electrodes, whereby said second non-conductive insulated gate field-effect transistor is employed as the active load for said first conductive insulated gate field-effect transistor.

3. The circuit of claim 2 further characterized by the channel region of each insulated gate field effect device being of the same conductivity type as the substrate of said insulated gate field effect device when there is no