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 is also employed in the present invention. The P-type insulated field-effect semiconductor device 30 includes a body or wafer 31 made of suitable semiconductor material, such as silicon. The silicon body or substrate 31 is doped in a conventional manner with N-type impurities, such as antimony, arsenic or phosphorous. Also formed in the silicon body 31 are P-type diffused regions 32 and 33, which extend to an upper surface 35 of the N-type silicon wafer 31. The P-type diffused regions 32 and 33 are formed in a conventional manner by diffusing a P-type impurity, such as boron or indium into the silicon body 11. An insulated layer 40 preferably of silicon dioxide is thermally grown on the surface 35 of the silicon body 31 and is located in part between the drain contact 36 and the source contact 37. A suitable metallic substance, such as aluminum, is then evaporated or otherwise deposited to form the drain contact 36 and the source contact 37. A metal gate 41 of preferably aluminum is disposed in contact with the portion of the insulated layer 40 located between the drain contact 36 and the source contact 37, such that the metal overlaps the inside edges of the diffused regions 32 and 33. Lead 36' is attached to the drain contact 36 and a lead 41' is attached to the gate 41. The source electrode 21 has a lead 21' attached thereto and connected to the substrate 31.

In practice, the external insulated gate field-effect semiconductor devices 10 and 30 are produced with relative facility and ease of operation. After the silicon substrate or wafer is prepared, it is oxidized by exposure to an oxygen-containing atmosphere at temperatures in the order of 1200 degrees centigrade. Thereupon, an array of holes is formed in the oxide by photolithographic techniques. Since the remaining oxide film acts as a barrier against the penetration of most donor and acceptor impurities, the contact areas can be diffused selectively into the holes which have been prepared in the oxide.

A second photoengraving operation is required to reopen the holes over the diffused regions for electrical contacts, since during the diffusion cycle, oxide is ordinarily regrown. The metal contacts for the source, gate and drain can be applied simultaneously by evaporating a metal film, usually aluminum, over the entire surface and removing the unwanted portions by a third photoengraving operation. The source is electrically connected to the substrate during the preparation of the device structure.

As shown in FIG. 3, the N-type external insulated gate field-effect semiconductor device 10, which is a majority carrier device by electron conduction, has a positive biasing potential Vds applied between the drain 20 and the source 21 with the drain 20 at a positive voltage and with the source 21 at ground. When current flows in the semiconductor device 10, it flows from the drain 20 to the source 21 through a path disposed therebetween adjacent the insulated layer 22 and parallel with the upper surface 14 of the silicon body 11. The path for the current Ids includes the N-diffused regions 12 and 13 with the portion of the P-type silicon body 11 therebetween. The flow of current Ids from the drain 20 to the source 21 is controlled by the potential applied to the gate 25 with respect to the source 21, which is at ground. In order for current Ids to flow or the device 10 to be rendered conductive, the applied potential Vgs between the gate 25 and the source 21 must be equal to or greater in magnitude than a critical positive potential Vgsc (see FIG. 9). When the voltage Vgs falls below the critical positive potential, no current will flow from the drain 20 to the source 21 and the device 10 is rendered non-conductive. The critical potential Vgsc required before the device 10 first starts to conduct can be regulated by varying the thickness of the insulated layer 22.

The P-type insulated gate field-effect semiconductor device 30 (FIG. 4), which is a majority carrier device by hole conduction, has a negative biasing potential Vds applied between the drain 31 and the source 37 with the drain 36 at a negative voltage and with the source 37' at ground. When current flows in the semiconductor device 30, it flows from the source 37 to the drain 36 through a path disposed therebetween adjacent the insulated layer 40 and parallel with the upper surface 35 of the silicon body 31. The path or channel for the current Ids includes the P-diffused regions 32 and 33 with the portion of the N-type silicon body 31' therebetween. The flow of current Ids from the source 37 to the drain 36 is controlled by the potential applied to the gate 41 with respect to the source 37', which is at ground. In order for current Ids to flow or the device 30 to be rendered conductive, the applied potential Vgs between the gate 41 and the source 37 must be equal to or more negative in magnitude than a critical negative potential V'gsc (see FIG. 10). When the voltage Vgs is less negative than the critical negative potential, no current will flow from the source 37 to the drain 36 and the device 31 is rendered non-conductive. The negative potential Vgsc required before the device 30 first starts to conduct can be regulated by varying the thickness of the insulated layer 40.

When an electric field is applied to the surface of an insulated field-effect semiconductor device, the mobile charge carriers within the semiconductor device are attracted to or repelled from the surface. In the event the field so applied is of adequate magnitude and of proper polarity, the resulting accumulation of carriers near the surface can result in the formation of an inversion layer or channel in which the majority carrier near the surface is of opposite type from that in the remainder of the semiconductor body.

By applying to the gate 25 of the N-type field-effect semiconductor device 10 (FIGS. 1, 1A and 3) a positive potential relative to the substrate 11 equal to or greater than the critical magnitude, an N-type inversion layer or channel now connects the N-diffused regions 12 and 13 for imparting a source-to-drain conductance thereto. In the complementary P-type field-effect semiconductor device 30 (FIGS. 2, 2A and 4), a negative potential is applied to the gate 41 of the critical magnitude to form a P-type inversion layer or channel between the P-diffused regions 32 and 33 to impart a drain-to-source conductance thereto. The transistor region between the inversion layer and the substrate functions like a P-N junction and remains reverse biased at all times. When the potential applied to a gate is less than the critical value, the impedance between the source and the drain is very high and corresponding to a reverse biased planar silicon diode.

The voltage applied to the drain of the field-effect semiconductor devices is of a polarity to reverse bias the diffused junction at the drain contact. Hence, a positive voltage is applied to the drain contact for diffused N-regions and a negative voltage is applied to the drain contact for diffused P-regions.

According to the present invention, an inverter circuit 50 (FIG. 5) employs the P-type insulated gate field-effect semiconductor device 30 and the complementary N-type insulated gate field-effect semiconductor device 10 to effect a switching operation without employing any passive components, such as a load resistor or some other passive load element. By connecting the sources 36 and 20 of the semiconductor devices 30 and 10, respectively, in common over conductors 51 and 52 and by connecting the gates 41 and 25 of the semiconductor devices 30 and 10, respectively, in common over conductors 53 and 54, the field-effect semiconductor device 30, a majority hole carrier device, is used as the active load for the field-effect semiconductor device, a majority electron carrier device. The converse is also true, since the field-effect semiconductor device 10, a majority electron carrier device, is used as the active load for the field-effect semiconductor device 30, a majority hole carrier device.

In the operation of the inverter circuit 50, an input signal Vi (FIGS. 5, 5A and 5B) is impressed on the gates 25 and 41 of the semiconductor devices 10 and 30,