Page:Gametronics Proceedings.djvu/51

 MK3861–PIO (Parallel Input/Output) contains 16 bits of I/O, programmable timer, and external interrupt. Used to expand I/O.

Two new devices being introduced are:

MK3870–a new +5v only, single chip microcomputer containing 2K ROM, 64 byte RAM, 32 bits of I/O, on board reset and oscillator circuitry, external interrupt, and enhanced programmable timer, all in 40 pin package for under $10!

Mk3871MK3871 [sic]–PIO (Parallel Input/Output) a new PIO device containing the new timer design and interrupt logic featured in the MK3870 for use in the 3850 series.

As this family grows, new devices will appear all aimed toward the common goal of reducing system cost through minimizing the number of IC's required to implement a given design. Some of the key features of the F8 parts discussed above are highlighted in Figs. 4–8 and again illustrate why the MOSTEK F8 is considered by many game designers to be the best microprocessor choice for today's games.

We have thus established that the microcomputer is the only way to go for serious game designs and that the MOSTEK F8 represents an excellent choice of combining economy, performance, and flexibility within a family of readily available parts. Now let's look at some examples of this F8 family in action spanning both pinball and video game applications.

Fig. 9 shows the general elements required in a coin actuated video game. The central computer determines that the proper coins have been inserted into the coin acceptor then proceeds to interpret the operators manipulation of the controls (joysticks, push buttons, keyboards, pots, etc.) and supply sound and update the displays and TV monitor when required. The computer thus acts much like a transducer in converting the control actuation into movement or changes on the video monitor.

A simple 2 chip (MK3850 and MK3851) F8 based, paddle type video game developed by a European company is shown in Fig. 10. The video display is refreshed out of a 4K x 4 memory (four MOSTEK MK4096 dynamic RAM's) and this act of display refresh also refreshes the dynamic RAM's. The output of the memory goes to a video shift register where it is converted from parallel to a serial train of binary data to be fed into a video summer circuit. The horizontal and vertical address counters provide a 128 x 128 format and normally address the memory except during those times when the F8 CPU switches the multiplexers to supply its own memory address. The writing of a single bit into the